Generally in a semiconductor integrated circuit device, a phase-locked loop is mounted in order to generate a processing clock of a logic circuit or generate a transmission signal clock. The phase-locked loop (PLL) mounted on the semiconductor integrated circuit device includes an analog circuit (particularly, voltage-controlled oscillator (VCO)). Therefore, a calibration technology of performing automatic adjustment such that the PLL satisfies desired characteristics is known.
For example, JP 2008-219513 A discloses a PLL calibration technology.